1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, concerns a semiconductor processing technique for the fabrication of field effect transistors which are configured to reduce the likelihood of punch through between the source and drain of the field effect transistors.
2. Description of the Related Art
The ever increasing scale of integration of integrated circuits has resulted in increasingly smaller device dimensions and has further resulted in device components being positioned closer and closer together in a semiconductor substrate. The close proximity of device structures results in problems in isolating device structures. For example, the demand for increasingly higher scales of integration of integrated circuits has resulted in field effect transistors where the source and drains of the transistors are positioned closer and closer together. In this particular circumstance, the close proximity to the source and the drain can result in electrical conduction between the source and drain that is not responsive to the formation of a conductive channel in the substrate as a result of activation of the gate of the transistor.
This particular phenomenon is known as punch through. Typically, punch through occurs as a result of the depletion region in the channel area of the field effect transistor resulting from the source and drain regions meeting with each other. This allows for electrical conduction of charge carriers between the source and drain regions of the transistor even in the absence of the application of voltage to a gate creating a conductive channel in the substrate. Once punch through occurs in the field effect transistor, the transistor is no longer operating in a desired manner which can affect the overall operation of the integrated circuit and can possibly even result in damage to the circuit.
To address the particular problems associated with punch through, various doping techniques for doping the channel region of the field effect transistor have been employed. It is well understood that increased dopant concentration in the channel region of the field effect transistor will limit the depletion region in the channel region such that the likelihood of punch through between the source and drain is reduced.
FIGS. 1A and 1B illustrate a typical technique for increasing the dopant concentration in a channel edge region and bottom of a source/drain region of a field effect transistor using a technique generally referred to as halo implant. As illustrated in FIG. 1A, after the formation of a gate stack 100, and prior to the formation of source and drain regions 102, 104 (FIG. 1B), doping ions are implanted into the channel edge region 105 and bottom of the source/drain region of the substrate 103 so as to increase the doping concentration of the channel edge region 105. Typically, boron atoms are implanted into an n-doped silicon substrate using well-known implantation techniques so as to define a region 106 of increased doping concentration in the channel region 105. Subsequent to the channel implant, the source region 102 and the drain region 104 are formed in a well-known manner resulting in the field effect transistor shown in FIG. 1B.
While the halo or pocket implant technique can be used for increasing the doping concentration in the channel edge region 105 between the source 102 and the drain 104 thereby reducing the likelihood of punch through, this technique does, however, also increase the amount of parasitic capacitance between the source 102 and the drain 104 and the substrate 103. In particular, there is an increase in the junction capacitance at the source 102 and the drain 104 of the field effect transistor such that the junction capacitance substantially contributes to the input capacitance of the transistor as a whole. Moreover since contact alignment limitations make it difficult to proportionally reduce the size of the source and drain regions in scaled down field effect transistors, the problem with increased junction capacitance is amplified even further.
As is understood in the art, a large input capacitance on a field effect transistor limits the switching speed of the device. In particular, the switching speed of the transistor is determined by the amount of time that is required to reconfigure the channel between a conducting state and an insulating state. Furthermore, the channel is reconfigured by adding or removing charge to and from the gate, the speed of which is dependent on the rise and fall times that the control voltage applied either across the source and gate or the drain and gate of the transistor. Thus, since the input capacitance of the transistor forms a part of an RC circuit which limits the rise and fall times of the control voltage, a relatively large input capacitance will result in a relatively slow switching speed. Hence, while halo or pocket implants are capable of reducing punch through, it is achieved at the cost of a slower device.
Another prior art technique for limiting punch through is illustrated in FIGS. 2A and 2B. In this approach, isolation regions 122 are formed in a semiconductor substrate 120 and an oxide layer 124 is grown over the active area 123. A masking layer 125 is then positioned on top of the oxide 124 and is patterned and etched in the manner shown in FIG. 2A. Subsequently, doping atoms, such as boron, are implanted through the oxide layer 124 so as to form a region 126 of increased doping concentration within the channel region 127 of the semiconductor substrate 120. Subsequently, the sacrificial oxide layer 124 is removed and a gate stack is formed on the upper surface of the substrate in the manner that is shown in FIG. 2B.
By implanting the boron directly into the substrate, the problems of increased junction capacitance occurring in the halo implant procedure is reduced. However, this technique of reducing punch through by increasing the doping concentration through direct implantation also has several shortcomings. In particular, the gate stack formation typically requires the growth of a gate oxide region after the removal of the sacrificial oxide layer 124. Gate oxide formation typically requires the use of a high temperature oxidation procedure which results in diffusion of the dopant atoms within the semiconductor substrate.
Specifically, the high temperature oxidation procedure used to grow a gate oxide 150 of a gate stack 152 typically results in diffusion of the dopant atoms in the doped region 126 in the channel region 127 such that the dopant atoms no longer have a retrograde profile (as represented by the dashed lines in FIG. 2B). In fact, the doping profile, i.e., the dopant concentration, is more uniform from the upper surface of the substrate 120 immediately adjacent the gate oxide 150 to the bottom of the channel region 127 adjacent the bottom surfaces of the source and drain regions 154, 156 formed in the substrate 120.
The non-retrograde doping profile typically results in decreased protection against punch through for very small dimension devices. In particular, the maximum doping concentration at the surface of the semiconductor substrate immediately adjacent the gate oxide is dictated by the desired threshold voltage. The desired threshold voltage is the voltage that must be applied to the gate in order to form a channel in the substrate 120 and thereby activate the device. Typically, this voltage is relatively low which results in a comparatively low doping concentration in the substrate 120 immediately underneath the gate oxide 150. Due to the diffusion of the implanted species in the channel region 127 as a result of the wet oxidation formation of the gate oxide, the doping concentration in the remainder of the channel region is comparable to the doping concentration immediately underneath the gate oxide which can be relatively ineffective at preventing punch through with devices exhibiting smaller geometries.
From the foregoing, it will be apparent that there is a need for smaller dimension field effect transistor configurations that are adapted to inhibit punch through in the channel regions. To this end, there is a need for device fabrication techniques whereby the channel region can be configured to inhibit punch through while still allowing for acceptable threshold voltages.